View SL15100ZC-XXXT_3777674.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 2.0, august 10, 2008 page 1 of 16 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax: (408) 855-0550 www.spectralinear.com sl15100 pro g rammable s p read s p ectrum clock generator ( sscg ) key features ? low power dissipation - 7.7ma-typ at 66mhz and vdd=3.3v - 6.8ma-typ at 66mhz and vdd=2.5v ? wide 2.5v to 3.3v +/-10% power supply range ? programmable outputs from 3 to 200mhz ? low jitter - 110ps at 66mhz ? programmable center or down spread modulation from 0.25 to 5.0% ? 8 to 48 mhz external crystal range ? 8 to 166 mhz external clock range ? integrated internal voltage regulator ? programmable pd#/oe/sson#/fs functions ? programmable cl at xin and xout pins ? programmable output rise and fall times ? programmable modulation frequency from 25 to 120 khz applications ? printers, mfps ? digital copiers ? nbpcs and lcd monitors ? routers, servers and switchers ? hdtv and dvd-r/w description the sl15100 a programmable low power spread spectrum clock generator (sscg) used for reducing electromagnetic interference (emi). the product is designed using spectralinear proprietary eproclock? programmable phase-locked loop (pll) and spread spectrum clock (ssc) technology to synthesize and modulate the input clock. the modulated clock can significantly reduce the measured emi levels, and leading to the compliance with regulatory agency requirements. the output clock frequency, spread %, output rise and fall times, crystal load, modulation frequency and pd#/oe/sson#/fs functions can be programmed to meet the needs of wide range of applications. the sl15100 operates from 2.5v to 3.3v power supply voltage range. the product is offered in 8-pin tssop package with commercial and industrial grades. refer to sl15300 for up to four (4) programmable clock outputs and for 1.8v power supply operation. benefits ? peak emi reduction of 8 to 16 db ? fast time-to-market ? cost reduction ? reduction of pcb layers ? eleminates the need for higher order crystals (xtals) and crystal oscillators (xos) block diagram
rev 2.0, august 10, 2008 page 2 of 16 sl15100 pin configuration 8-pin tssop pin description pin number pin name pin type pin description 1 vdd power positive power supply. 2 xout output crystal or ceramic resonator output pin. leave this pin unconnected (floating) if external clock is used at pin-3. 3 xin/clkin input crystal, ceramic resonator or external clock input pin. 4 pd#/oe input user programmable pd# or oe control pin. power down (pd#-active low): if pd#=0(low), the device is powered down and both ssclk and refout outputs are weakly pulled low to vss. output enable (oe- active high): if oe=1(high), the ssclk and refout outputs are enabled. pd# or oe is weakly pulled high to vdd. 5 vss power power supply ground. 6 ssclk1 or refclk1 output this pin can be programmed as ssclk1 or refclk1. 7 ssclk2 or refclk2 output this pin can be programmed as ssclk2 or refclk2. 8 sson#/fs input programmable sson# or frequency select (fs) control pin. if sscg# function is programmed: spread-on=0(low) or spread-off=1(high). if fs function is programmed: the clock frequencies can be switched between two sets of frequencies as programmed. sson# or fs is weakly pulled low to vss.
rev 2.0, august 10, 2008 page 3 of 16 sl15100 general description the primary source of emi from digital circuits is the system clock and all the other synchronous clocks and control signals derived from the system clock. the well know techniques of filtering (suppression) and shielding (containment), while effective, can cost money, board space and longer development time. a more effective and efficient technique to reduce emi is spread spectrum clock generator (sscg) technique. instead of using constant clock frequency, the sscg technique modulates (spreads) the system clock with a much smaller frequency, to reduce emi emissions at its source: the system clock. the sl15100 is designed using spectralinear proprietary programmable eproclock? phase-locked loop (pll) and spread spectr um technologies (sst) to synthesize and modulate (spread) the system clock such that the energy is spread out over a wider bandwidth. this reduces the peak value of the radiated emissions at the fundamental and the harmonics. this reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time-to-market without degrading system perfor- mance. the sl15100 operates with both 3.3v and 2.5v power supply voltages. refer to sl15l100 for 1.8v power supply operation. the sl15100 is available in 8-pin tssop package with extended commercial temperature range of 0 to +85 c and industrial temperature range of ?40 to +85c. input frequency range the input frequency range is from 8.0 to 48.0 mhz for crystals and ceramic resonators. if an external clock is used, the input frequency range is from 8 to 166 mhz. output frequency range and outputs the two (2) outputs can be programmed as ssclk or refclk. ssclk output can be synthesized to any value from 3 to 200 mhz with spread based on valid input frequency. the spread at ssclk pins can be stopped by sson# input control pin, if sson# pin is high (vdd), the frequency at this pin is the synthesized nominal value of the input frequency and there is no spread. refout is the buffered output of the oscillator and is the same frequency as the input frequency without spread. however, refout value can also be divided by using the output dividers from 2 to 32. the second programmable output (ssclk2) can be used to generate a copy of ssclk1 (fanout of 2) or the same ssclk frequency can be divided from 2 to 32. in this case, the spread % value is the same as the original programmed spread % value. by using only first order crystals, sl15100 can synthesize output frequency up to 200 mhz, eliminating the need for higher order crystals (xtals) and crystal oscillators (xos). this reduces the cost while improving the system clock accuracy, performance and reliability. programmable cl (crystal load) the sl15100 provides programmable on-chip capacitors at xin/clkin (pin-3) and xout (pin-2). the resolution of this programmable capacitor is 6-bits with lsb value of 0.5pf. when all bits are off the pin capacitance is cxin=cxout =8.5pf (minimum value). when all bits are on the pin capacitance is cxin=cxout=40pf (maximum value). the values of c xin and c xout based on the c l (crystal load capacitor) can be calculated as: c xin =c xout =2c l -c pcb . refer to the page-13 for additional information on crystal load (c l ). in addition, if an external clock is used, the capacitance at pin-3 (clkin) can programmed to control the edge rate of this input clock, providing additional emi control. programmable modulation frequency the spread spectrum clock (ssc) modulation default value is 31.5 khz. the higher value of up to120 khz can also be programmed. less than 25 khz modulation frequency is not recommended to stay out of the range audio frequency bandwidth since this frequency could be detected as a noise by the audio receivers within the vicinity. programmable spread percent (%) the spread percent (%) value is programmable from +/- 0.25% to +/-2.5% (center spread) or -0.5% to -5.0% (down spread) for all ssclk frequencies. it is possible to program smaller or larger non-standard values of spread percent. contact sli if these non-standard spread percent values are required in the application. sson# or function select (fs) the sl15100 pin-8 can be programmed as either sson# to enable or disable the programmed spread percent value or as function select (fs). if sson# is used, when this pin is pulled high (vdd), the spread is stopped and the frequency is the nominal value without spread. if low (gnd), the frequency is the nominal value with the spread. if fs function is used, the output pins can be programmed for different set of frequencies or spread % as selected by fs. ssclk value can be any frequency from 3 to 200mhz, but the spread % is the same percent value. refout is the same frequency as the input reference clock or divide by from 2 to 32 without spread. the set of frequencies in table 1 is given as en example, using 48mhz crystal. the sl15100 also allows a fan-out of 2, meaning that pins 6 and 7 can be programmed to the same frequencies with or without spread such that f1=f2 and f3=f4. fs (pin-8) ssclk1 (pin-6) refclk2 (pin-7) 0 f1= 66mhz, +/-1% f2= 48mhz 1 f3 =125mhz,+/-3% f4= 24mhz table 1. frequency selection (fs) power down (pd#) or output enable (oe) the sl15100 pin-4 can be programmed as either pd# or oe. pd# powers down the entire chip whereas oe only disables the output buffers to hi-z.
rev 2.0, august 10, 2008 page 4 of 16 sl15100 absolute maximum ratings description condition min max unit supply voltage, vdd -0.5 4.2 v all inputs and outputs -0.5 vdd+0.5 v ambient operating temperature in operation, c-grade 0 85 c ambient operating temperature in operation, i-grade -40 85 c storage temperature no power is applied -65 150 c junction temperature in operation, power is applied - 125 c soldering temperature - 260 c esd rating (human body model) jedec22-a114d -4,000 4,000 v esd rating (charge device model) jedec22-c101c -1,500 1,500 v esd rating (machine model) jedec22-a115d -250 250 v dc electrical characteristics (c-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=15pf and ambient temperature range 0 to +85 deg c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.97 3.3 3.63 v input low voltage vil cmos level, pins 4 and 8 0 - 0.3vdd v input high voltage vih cmos level, pins 4 and 8 0.7vdd - vdd v output high voltage voh1 ioh=10ma , pins 6 and 7 vdd-0.5 - - v output low voltage vol1 iol=10ma, pins 6 and 7 - - 0.5 v input high current iih vin=vdd, pins 4 and 8 if no pull-up/down resister used - - 10 a input low current iil vin=gnd, pins 4 and 8 if no pull-up/down resister used - - 10 a pull-up/down resistors rpu/d vin=vdd or gnd 100 150 300 k ? operating supply current idd fin=30mhz, refclk=30mhz ssclk=66mhz, pd#/oe=vdd sson#=gnd, cl=0 - 7.7 9.2 ma standby current isbc pd#=gnd - 90 120 a output leakage current iol pins 6 and 7 -10 - 10 a minimum setting value - 7 - pf maximum setting value - 38 - pf programmable input capacitance at pins 2 and 3 pcin pcout resolution (programming steps) - 0.5 - pf input capacitance cin2 pins 4 and 8 - 4 6 pf load capacitance cl ssclk/refclk , pins 6 and 7 - - 15 pf
rev 2.0, august 10, 2008 page 5 of 16 sl15100 ac electrical characteristics (c-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=15pf and ambient temperature range 0 to +85 deg c parameter symbol condition min typ max unit input frequency range fin1 crystal or ceramic resonator 8 - 48 mhz input frequency range fin2 external clock 8 - 166 mhz output frequency range fout1 ssclk 3 - 200 mhz output frequency range fout2 refclk, crystal or resonator input 0.25 - 48 mhz output frequency range fout3 refclk, clock input 0.25 - 166 mhz output duty cycle dc1 ssclk 45 50 55 % output duty cycle dc2 refclk 45 50 55 % input duty cycle dcin clock input, pin 3 40 50 60 % output rise/fall time tr/f1 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 4.00 4.80 ns output rise/fall time tr/f2 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 2.00 2.40 ns output rise/fall time tr/f3 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 1.40 1.70 ns output rise/fall time tr/f4 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 1.10 1.35 ns output rise/fall time tr/f5 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 0.85 1.00 ns output rise/fall time tr/f6 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 0.70 0.85 ns output rise/fall time tr/f7 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 0.55 0.67 ns cycle-to-cycle jitter (ssclk ? pin 7) ccj1 clkin=ssclk=166mhz, 2%spread refclk=off - 90 120 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj2 clkin=ssclk=66mhz, 2%spread refclk=off - 100 130 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj3 clkin=ssclk=33mhz, 2%spread refclk=off - 120 160 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj4 clkin=ssclk=166mhz, 2%spread refclk=on - 100 130 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj5 clkin=ssclk=66mhz, 2%spread refclk=on - 105 140 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj6 clkin=ssclk=33mhz, 2%spread refclk=on - 180 240 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj7 clkin=ssclk=166mhz, 2%spread refclk=on - 80 100 ps
rev 2.0, august 10, 2008 page 6 of 16 sl15100 cycle-to-cycle jitter (ssclk ? pin 6) ccj8 clkin=ssclk=66mhz, 2%spread refclk=on - 100 130 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj9 clkin=ssclk=33mhz, 2%spread refclk=on - 135 180 ps power-down time tpd time from pd# falling edge to hi-z at outputs (asynchronous) - 150 350 ns power-up time (crystal or clock) tpu time from pd# rising edge to valid frequency at outputs (asynchronous) - 3.5 5.0 ms power supply ramp time tpsr time for vdd reaching minimum specified value and monolithic power supply ramp - - 12 ms output enable time toe time from oe falling edge to hi-z at outputs (asynchronous) - 180 350 ns output disable time tod time from oe falling edge to hi-z at outputs (asynchronous) - 180 350 ns spread percent range spr ssclk-1/2 outputs 0.25 - 5.0 % spread percent variation ss% variation of programmed spread % -15 - 15 % modulation frequency fmod programmable, 31.5 khz standard 25 31.5 120 khz dc electrical characteristics (c-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=15pf and ambient temperature range 0 to +85 deg c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.25 2.5 2.75 v input low voltage vil cmos level, pins 4 and 8 0 - 0.3v dd v input high voltage vih cmos level, pins 4 and 8 0.7v dd - v dd v output high voltage voh1 ioh=6ma , pins 6 and 7 v dd -0.5 - - v output low voltage vol1 iol=6ma, pins 6 and 7 - - 0.5 v input high current iih vin=vdd, pins 4 and 8 if no pull-up/down resister used - - 10 a input low current iil vin=gnd, pins 4 and 8 if no pull-up/down resister used - - 10 a pull-up/down resistors rpu/d vin=vdd or gnd 100 150 300 k ? operating supply current idd fin=30mhz, refclk=30mhz ssclk=66mhz, pd#/oe=vdd sson#=gnd, cl=0 - 6.8 8.1 ma standby current isbc pd#=gnd - 90 120 a output leakage current iol pins 6 and 7 -10 - 10 a minimum programming value - 7 - pf maximum programming value - 38 - pf programmable input capacitance at pins 2 and 3 cxin cxout resolution (programming steps) - 0.5 - pf
rev 2.0, august 10, 2008 page 7 of 16 sl15100 input capacitance cin2 pins 4 and 8 - 4 6 pf load capacitance cl ssclk/refclk , pins 6 and 7 - - 15 pf ac electrical characteristics (c-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=15pf and ambient temperature range 0 to +85 deg c parameter symbol condition min typ max unit input frequency range fin1 crystal or ceramic resonator 8 - 48 mhz input frequency range fin2 external clock 8 - 166 mhz output frequency range fout1 ssclk 3 - 200 mhz output frequency range fout2 refclk, crystal or resonator input 0.25 - 48 mhz output frequency range fout3 refclk, clock input 0.25 - 166 mhz output duty cycle dc1 ssclk 45 50 55 % output duty cycle dc2 refclk 45 50 55 % input duty cycle dcin clock input, pin 3 40 50 60 % output rise/fall time tr/f1 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 4.80 5.80 ns output rise/fall time tr/f2 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 2.60 3.10 ns output rise/fall time tr/f3 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 1.80 2.20 ns output rise/fall time tr/f4 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 1.40 1.70 ns output rise/fall time tr/f5 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 1.10 1.35 ns output rise/fall time tr/f6 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 0.90 1.10 ns output rise/fall time tr/f7 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 0.70 0.85 ns cycle-to-cycle jitter (ssclk ? pin 7) ccj1 clkin=ssclk=166mhz, 2%spread refclk=off - 100 130 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj2 clkin=ssclk=66mhz, 2%spread, refclk=off - 110 140 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj3 clkin=ssclk=33mhz, 2%spread, refclk=off - 130 170 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj4 clkin=ssclk=166mhz, 2%spread refclk=on - 110 140 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj5 clkin=ssclk=66mhz, 2%spread, refclk=on - 115 150 ps
rev 2.0, august 10, 2008 page 8 of 16 sl15100 cycle-to-cycle jitter (ssclk ? pin 7) ccj6 clkin=ssclk=33mhz, 2%spread, refclk=on - 200 260 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj7 clkin=ssclk=166mhz, 2%spread, refclk=on - 90 110 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj8 clkin=ssclk=66mhz, 2%spread refclk=on - 110 140 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj9 clkin=ssclk=33mhz, 2%spread refclk=on - 150 200 ps power-down time tpd time from pd# falling edge to hi-z at outputs (asynchronous) - 180 350 ns power-up time (crystal or clock) tpu time from pd# rising edge to valid frequency at outputs (asynchronous) - 3.5 5.0 ms power supply ramp time tpsr time for vdd reaching minimum specified value and monolithic power supply ramp - - 12 ms output enable time toe time from oe falling edge to hi-z at outputs (asynchronous) - 180 350 ns output disable time tod time from oe falling edge to hi-z at outputs (asynchronous) - 180 350 ns spread percent range spr ssclk-1/2 0.25 - 5.0 % spread percent variation ss% variation of programmed spread % -15 - 15 % modulation frequency fmod programmable, 31.5 khz standard 25 31.5 120 khz dc electrical characteristics (i-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=15p f and ambient temperature range -40 to +85 deg c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.97 3.3 3.63 v input low voltage vil cmos level, pins 4 and 8 0 - 0.3v dd v input high voltage vih cmos level, pins 4 and 8 0.7v dd - v dd v output high voltage voh1 ioh=8ma , pins 6 and 7 v dd -0.5 - - v output low voltage vol1 iol=8ma, pins 6 and 7 - - 0.5 v input high current iih vin=vdd, pins 4 and 8 if no pull-up/down resister used - - 15 a input low current iil vin=gnd, pins 4 and 8 if no pull-up/down resister used - - 15 a pull-up or down resisto r rpu/d vin=vdd or gnd 100 150 300 k ? operating supply curren t idd fin=30mhz, refclk=30mhz ssclk=66mhz, pd#/oe=vdd sson#=gnd, cl=0 - 8.0 9.6 ma
rev 2.0, august 10, 2008 page 9 of 16 sl15100 standby current isbc pd#=gnd - 90 120 a output leakage current iol pins 6 and 7 -15 - 15 a minimum setting value - 7 - pf maximum setting value - 38 - pf programmable input capacitance at pins 2 and 3 cxin cxout resolution (programming steps) - 0.5 - pf input capacitance cin2 pins 4 and 8 - 4 7 pf load capacitance cl ssclk/refclk , pins 6 and 7 - - 15 pf ac electrical characteristics (i-grade) unless otherwise stated vdd= 3.3v+/- 10%, cl=15p f and ambient temperature range -40 to +85 deg c parameter symbol condition min typ max unit input frequency range fin1 crystal or ceramic resonator 8 - 48 mhz input frequency range fin2 external clock 8 - 166 mhz output frequency range fout1 ssclk 3 - 200 mhz output frequency range fout2 refclk, crystal or resonator input 0.25 - 48 mhz output frequency range fout3 refclk, clock input 0.25 - 166 mhz output duty cycle dc1 ssclk 45 50 55 % output duty cycle dc2 refclk 45 50 55 % input duty cycle dcin clock input, pin 3 40 50 60 % output rise/fall time tr/f1 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 4.00 4.80 ns output rise/fall time tr/f2 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 2.00 2.40 ns output rise/fall time tr/f3 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 1.40 1.70 ns output rise/fall time tr/f4 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 1.10 1.35 ns output rise/fall time tr/f5 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 0.85 1.00 ns output rise/fall time tr/f6 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 0.70 0.85 ns output rise/fall time tr/f7 programmable, vdd=3.3 cl=15pf, 20 to 80% of vdd - 0.55 0.67 ns cycle-to-cycle jitter (ssclk ? pin 7) ccj1 clkin=ssclk=166mhz, 2%spread refclk=off - 100 135 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj2 clkin=ssclk=66mhz, 2%spread refclk=off - 110 145 ps
rev 2.0, august 10, 2008 page 10 of 16 sl15100 cycle-to-cycle jitter (ssclk ? pin 7) ccj3 clkin=ssclk=33mhz, 2%spread refclk=off - 130 175 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj4 clkin=ssclk=166mhz, 2%spread refclk=on - 110 145 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj5 clkin=ssclk=66mhz, 2%spread refclk=on - 115 155 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj6 clkin=ssclk=33mhz, 2%spread refclk=on - 190 255 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj7 clkin=ssclk=166mhz, 2%spread refclk=on - 90 115 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj8 clkin=ssclk=66mhz, 2%spread refclk=on - 110 145 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj9 clkin=ssclk=33mhz, 2%spread refclk=on - 145 195 ps power-down time tpd time from pd# falling edge to hi-z at outputs (asynchronous) - 150 350 ns power-up time (crystal or clock) tpu time from pd# rising edge to valid frequency at outputs (asynchronous) - 3.5 5.0 ms power supply ramp time tpsr time for vdd reaching minimum specified value and monolithic power supply ramp - - 12 ms output enable time toe time from oe falling edge to hi-z at outputs (asynchronous) - 150 350 ns output disable time tod time from oe falling edge to hi-z at outputs (asynchronous) - 150 350 ns spread percent range spr ssclk-1/2 0.25 - 5.0 % spread percent variation ss% variation of programmed spread % -20 - 20 % modulation frequency fmod programmable, 31.5 khz standard 25 31.5 120 khz dc electrical characteristics (i-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=15p f and ambient temperature range -40 to +85 deg c description symbol condition min typ max unit operating voltage vdd vdd+/-10% 2.25 2.5 2.75 v input low voltage vil cmos level, pins 4 and 8 0 - 0.3vdd v input high voltage vih cmos level, pins 4 and 8 0.7vdd - vdd v output high voltage voh1 ioh=6ma , pins 6 and 7 vdd-0.4 - - v output low voltage vol1 iol=6ma, pins 6 and 7 - - 0.4 v input high current iih vin=vdd, pins 4 and 8 if no pull-up/down resister used - - 15 a input low current iil vin=gnd, pins 4 and 8 if no pull-up/down resister used - - 15 a
rev 2.0, august 10, 2008 page 11 of 16 sl15100 pull-up or down resistors rpu/d vin=vdd or gnd 100 150 300 k ? operating supply current idd fin=30mhz, refclk=30mhz ssclk=66mhz, pd#/oe=vdd sson#=gnd, cl=0 - 7.0 8.4 ma standby current isbc pd#=gnd - 90 120 a output leakage current iol pins 6 and 7 -10 - 10 a minimum setting value - 7 - pf maximum setting value - 38 - pf programmable input capacitance at pins 2 and 3 cxin cxout resolution (programming steps) - 0.5 - pf input capacitance cin2 pins 4 and 8 - 4 7 pf load capacitance cl ssclk/refclk , pins 6 and 7 - - 15 pf ac electrical characteristics (i-grade) unless otherwise stated vdd= 2.5v+/- 10%, cl=15p f and ambient temperature range -40 to +85 deg c parameter symbol condition min typ max unit input frequency range fin1 crystal or ceramic resonator 8 - 48 mhz input frequency range fin2 external clock 8 - 166 mhz output frequency range fout1 ssclk 3 - 200 mhz output frequency range fout2 refclk, crystal or resonator input 0.25 - 48 mhz output frequency range fout3 refclk, clock input 0.25 - 166 mhz output duty cycle dc1 ssclk 45 50 55 % output duty cycle dc2 refclk 45 50 55 % input duty cycle dcin clock input, pin 3 40 50 60 % output rise/fall time tr/f1 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 4.80 5.80 ns output rise/fall time tr/f2 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 2.60 3.10 ns output rise/fall time tr/f3 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 1.80 2.20 ns output rise/fall time tr/f4 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 1.40 1.70 ns output rise/fall time tr/f5 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 1.10 1.35 ns output rise/fall time tr/f6 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 0.90 1.10 ns output rise/fall time tr/f7 programmable, vdd=2.5 cl=15pf, 20 to 80% of vdd - 0.70 0.85 ns cycle-to-cycle jitter (ssclk ? pin 7) ccj1 clkin=ssclk=166mhz, 2%spread refclk=off - 115 150 ps
rev 2.0, august 10, 2008 page 12 of 16 sl15100 cycle-to-cycle jitter (ssclk ? pin 7) ccj2 clkin=ssclk=66mhz, 2%spread refclk=off - 125 160 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj3 clkin=ssclk=33mhz, 2%spread refclk=off - 125 160 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj4 clkin=ssclk=166mhz, 2%spread refclk=on - 145 185 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj5 clkin=ssclk=66mhz, 2%spread refclk=on - 125 160 ps cycle-to-cycle jitter (ssclk ? pin 7) ccj6 clkin=ssclk=33mhz, 2%spread refclk=on - 215 280 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj7 clkin=ssclk=166mhz, 2%spread refclk=on - 105 130 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj8 clkin=ssclk=66mhz, 2%spread refclk=on - 125 160 ps cycle-to-cycle jitter (ssclk ? pin 6) ccj9 clkin=ssclk=33mhz, 2%spread refclk=on - 165 220 ps power-down time tpd time from pd# falling edge to hi-z at outputs (asynchronous) - 180 350 ns power-up time (crystal or clock) tpu time from pd# rising edge to valid frequency at outputs (asynchronous) - 3.5 5.0 ms power supply ramp time tpsr time for vdd reaching minimum specified value and monolithic power supply ramp - - 12 ms output enable time toe time from oe falling edge to hi-z at outputs (asynchronous) - 180 350 ns output disable time tod time from oe falling edge to hi-z at outputs (asynchronous) - 180 350 ns spread percent range spr ssclk-1/2 0.25 - 5.0 % spread percent variation ss% variation of programmed spread % -20 - 20 % modulation frequency fmod programmable, 31.5 khz standard 25 31.5 120 khz
rev 2.0, august 10, 2008 page 13 of 16 sl15100 external components & design considerations typical application schematic comments and recommendations decoupling capacitor: a decoupling capacitor of 0.1 f must be used between vdd and vss on the pins 1 and 5. place the capacitor on the component side of the pcb as close to the vdd pin as possible. the pcb trace to the vdd pin and to the gnd via should be kept as short as possible do not use vias between the decoupling capacitor and the vdd pin. series termination resistor : a series termination resistor is recommended if the distance between the output (ssclk) and the load is over 1 ? inch. the nominal impedance of the ssclk output is about 30 ? . use 20 ? resistor in series with the output to terminate 50 ? trace impedance and place 20 ? resistor as close to the ssclk output as possible. crystal and crystal load: use only parallel resonant fundamental crystals. do not use higher overtone crystals. to meet the crystal initial accuracy specification (in ppm); the internal on-chip programmable capacitors pcin and pcout must be programmed to match the crystal load requirement. these values are given by the formula below: pcin(pf) =pcout(pf)= [(cl(pf) ? cp(pf)/2)] x 2 where cl is crystal load capacitor as given by the crysta l datasheet and cp(pf) is the compensation factor for the total parasitic capacitance at xin or xout pin including pcb related parasitic capacitance. as an example; if a crystal with cl=18pf is used and cp=4pf, by using the above formula, pcin=pcout=[(18-(4/2)] x 2 = 32pf. programming pcin and pcout to 32pf assures that this crystal sees an equivalent load of 18pf and no other external crystal load capacitor is needed. deviating from the crystal load specification could cause an increase in frequency accuracy in ppm. refer to the table 5 for the recommended crystal specifications.
rev 2.0, august 10, 2008 page 14 of 16 sl15100 recommended external crystal specifications parameter description min typ max unit comments fnom nominal crystal frequency range 8 - 48 mhz fundamental mode ? at cut cl nominal crystal load 6 12 18 pf load for +/-0 ppm fo resonance value r1,1 equivalent series resistance 20 40 100 ohm f-range: 8.0 to 12.999 mhz r1,2 equivalent series resistance 12.5 25 60 ohm f-range: 13.0 to 19.999 mhz r1,3 equivalent series resistance 10 20 50 ohm f-range: 20.0 to 48.000 mhz dl1,1 crystal drive level - - 200 w f-range: 8.0 to 19.999 mhz dl1,2 crystal drive level - - 150 w f-range: 20.0 to 48.000 mhz co1 shunt capacitance - 4 5.4 pf smd xtals co2 shunt capacitance - 5 7.2 pf through hole (leaded) xtals table 5. recommended crystal specifications
rev 2.0, august 10, 2008 page 15 of 16 sl15100 package outline and package dimensions 8-pin tssop package (173 mil) thermal characteristics parameter symbol condition min typ max unit ja1 still air - 110 - c/w ja2 1m/s air flow - 100 - c/w thermal resistance junction to ambient ja3 3m/s air flow - 80 - c/w thermal resistance junction to case jc independent of air flow - 35 - c/w
rev 2.0, august 10, 2008 page 16 of 16 sl15100 ordering information [1] ordering number [2] marking shipping package package temperature sl15100zc-xxx tbd tube 8-pin tssop 0 to 85c SL15100ZC-XXXT tbd tape and reel 8-pin tssop 0 to 85c sl15100zi-xxx tbd tube 8-pin tssop -40 to 85c sl15100zi-xxxt tbd tape and reel 8-pin tssop -40 to 85c notes: 1. all sli products are rohs compliant. 2. ?xxx? is ?dash? number and will be assigned by sli for the final programmed samples or production the units based on the each customer programming requirements. while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. thi s product is intended for use in normal commercial applications and is not warranted not is it intended for use in life support, critical medical instruments, or any other application requiring extended temperat ure range, high reliability, or any other extraordinary enviro nmental requirements unless pursuant to additional processing by spectra linear inc., and an expressed written agreement by spectra linear inc. spectra linear inc. reserves the right to change any circuitry or specification without notice.

▲Up To Search▲

Price & Availability of SL15100ZC-XXXT

	To Download SL15100ZC-XXXT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .